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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State Non-Inverting Transparent Latch
High-Performance Silicon-Gate CMOS
The MC54/74HC373A is identical in pinout to the LS373. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high-impedance state. Thus, data may be latched even when the outputs are not enabled. The HC373A is identical in function to the HC573A which has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout. The HC373A is the non-inverting version of the HC533A. * * * * * * Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 186 FETs or 46.5 Equivalent Gates LOGIC DIAGRAM
D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 3 4 7 8 13 14 17 18 2 5 6 9 12 15 16 19 Q0 Q1 Q2
MC54/74HC373A
J SUFFIX CERAMIC PACKAGE CASE 732-03
1
20
20 1 20 1
N SUFFIX PLASTIC PACKAGE CASE 738-03 DW SUFFIX SOIC PACKAGE CASE 751D-04 SD SUFFIX SSOP PACKAGE CASE 940C-03 DT SUFFIX TSSOP PACKAGE CASE 948E-02
20 1 20 1
ORDERING INFORMATION Ceramic MC54HCXXXAJ Plastic MC74HCXXXAN SOIC MC74HCXXXADW SSOP MC74HCXXXASD TSSOP MC74HCXXXADT
PIN ASSIGNMENT
OUTPUT ENABLE Q0 D0 D1 Q3 Q4 Q5 Q6 Q7 PIN 20 = VCC PIN 10 = GND NONINVERTING OUTPUTS Q1 Q2 D2 D3 Q3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 LATCH ENABLE
LATCH ENABLE OUTPUT ENABLE
11 1
FUNCTION TABLE
Inputs Output Enable L L L H Latch Enable H H L X D H L X X Output Q H L No Change Z
3/97
(c) Motorola, Inc. 1997
II I I IIIIIIIIIIIIIII IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II I I IIIIIIIIIIIIIII IIIIIIIIIIIIII II II I IIIIIIIIIIIIIII IIIIIIIIIIIIIII II I II IIIIIIIIIIIIIII II IIIIII II IIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIII
Design Criteria Value 46.5 1.5 5.0 Units ea ns Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product W pJ 0.0075 * Equivalent to a two-input NAND gate. 1
X = Don't Care Z = High Impedance
REV 7
MC54/74HC373A
IIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I I I II I I I I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I III I I I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I II I I I I I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII III I III I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III III I I II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I
II I I I I I I I IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I III I I I I I II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 35 75 750 500 450 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package SSOP or TSSOP Package Storage Temperature mW Tstg TL - 65 to + 150 260 300
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v
v
_C _C
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC, SSOP or TSSOP Package) (Ceramic DIP)
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C SSOP or TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Parameter
Min 2.0 0
Max 6.0
Unit V V
DC Supply Voltage (Referenced to GND)
Vin, Vout TA
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
VCC
- 55 0 0 0
+ 125 1000 500 400
_C
ns
tr, tf
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol VIH
Parameter
Test Conditions
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0
- 55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9
v 85_C v 125_C
1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.2 3.7 5.2
Unit V
Minimum High-Level Input Voltage
Vout = VCC - 0.1 V |Iout| 20 A
v v v
VIL
Maximum Low-Level Input Voltage
Vout = 0.1 V |Iout| 20 A
V
VOH
Minimum High-Level Output Voltage
Vin = VIH |Iout| 20 A Vin = VIH
V
|Iout| |Iout| |Iout|
v 2.4 mA v 6.0 mA v 7.8 mA
2.48 3.98 5.48
2.34 3.84 5.34
MOTOROLA
2
High-Speed CMOS Logic Data DL129 -- Rev 6
II I II I I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I II I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIII I I II I I I I IIIIIIIIIIII II I I III I I I I I I II I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I II I I I II I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I I II I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D). NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
High-Speed CMOS Logic Data DL129 -- Rev 6 Symbol Symbol S bl VOL tPZL tPZH tPLZ tPHZ tPLH tPHL tPLH tPHL tTLH tTHL CPD Cout ICC Iin IOZ Cin Maximum Quiescent Supply Current (per Package) Maximum Three-State Leakage Current Maximum Input Leakage Current Maximum Low-Level Output Voltage Power Di i i C P Dissipation Capacitance (P E bl d O i (Per Enabled Output)* )* Maximum Three-State Output Capacitance (Output in High-Impedance State) Maximum Input Capacitance Maximum Output Transition Time, Any Output (Figures 1 and 5) Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) Maximum Propagation Delay, Latch Enable to Q (Figures 2 and 5) Maximum Propagation Delay, Input D to Q (Figures 1 and 5) Parameter Parameter P Vin = VIL Vin = VIL |Iout| 20 A
* Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout = 0 A
|Iout| |Iout| |Iout| Vin = VCC or GND
v
Test Conditions
3
v 2.4 mA v 6.0 mA v 7.8 mA
VCC V
VCC V
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
6.0
6.0
6.0
3.0 4.5 6.0
2.0 4.5 6.0
- 55 to 25_C
- 55 to 25_C
Typical @ 25C, VCC = 5.0 V
0.5
0.1
0.26 0.26 0.26
150 100 30 26
150 100 30 26
140 90 28 24
125 80 25 21
4.0
0.1 0.1 0.1
15
10
60 23 12 10
Guaranteed Limit
Guaranteed Limit
v 85_C v 125_C
v 85_C v 125_C
5.0
1.0
0.33 0.33 0.33
190 125 38 33
190 125 38 33
175 120 35 30
155 110 31 26
0.1 0.1 0.1
15
10
75 27 15 13
40
36
MC54/74HC373A
1.0
10
225 150 45 38
225 150 45 38
210 140 42 36
190 130 38 32
160
0.4 0.4 0.4
0.1 0.1 0.1
15
10
90 32 18 15
MOTOROLA Unit Ui Unit A A A pF pF pF F ns ns ns ns ns V
I II I I I I I I I I I I IIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIII I I I I I I I II I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I II I I I I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I I I I I I I I IIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIII I I I I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
MOTOROLA
MC54/74HC373A
Symbol S bl
OUTPUT ENABLE
INPUT D
tr, tf
tsu
tw
th
Q
Q
Q
tPLH
Maximum Input Rise and Fall Times
Minimum Pulse Width, Latch Enable
Minimum Hold Time, Latch Enable to Input D
Minimum Setup Time, Input D to Latch Enable
tr
50%
tTLH
50%
1.3 V
90% 50% 10%
90% 50% 10%
Figure 3.
Figure 1.
tPZL
tPZH
tPHZ
tPLZ
Parameter P
tf
10%
90%
tPHL
tTHL
SWITCHING WAVEFORMS
HIGH IMPEDANCE
VOH
VOL
HIGH IMPEDANCE
GND
VCC
GND
VCC
Fig. Fi
4 1 2 4 4 LATCH ENABLE LATCH ENABLE VCC Volts 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 INPUT D Q - 55 to 25_C Min 25 20 5.0 5.0 5.0 5.0 5.0 5.0 60 23 12 10 50% 1000 800 500 400 Max 50% tw tPLH 50% Min 30 25 6.0 6.0 5.0 5.0 50 5.0 75 27 15 13 tsu
Guaranteed Limit
Figure 4.
Figure 2.
v 85_C
tPHL
VALID
1000 800 500 400
High-Speed CMOS Logic Data DL129 -- Rev 6 Max 50% th Min 40 30 8.0 7.0 5.0 5.0 5.0 5.0 90 32 18 15
v 125_C
1000 800 500 400
Max
GND
VCC
GND
GND VCC VCC Unit Ui ns ns ns ns
MC54/74HC373A
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST DEVICE UNDER TEST TEST POINT OUTPUT CL* 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL*
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 5.
Figure 6.
EXPANDED LOGIC DIAGRAM
D0 3 D Q D1 4 D Q D2 7 D Q D3 8 D Q D4 13 D Q D5 14 D Q D6 17 D Q D7 18 D Q
LE 11
LE
LE
LE
LE
LE
LE
LE
1 2 Q0 5 Q1 6 Q2 9 Q3 12 Q4 15 Q5 16 Q6 19 Q7
High-Speed CMOS Logic Data DL129 -- Rev 6
5
MOTOROLA
MC54/74HC373A
OUTLINE DIMENSIONS
J SUFFIX CERAMIC PACKAGE CASE 732-03 ISSUE E
B A F C L
DIM A B C D F G H J K L M N NOTES: 1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONS A AND B INCLUDE MENISCUS. MILLIMETERS MIN MAX 23.88 25.15 6.60 7.49 3.81 5.08 0.38 0.56 1.40 1.65 2.54 BSC 0.51 1.27 0.20 0.30 3.18 4.06 7.62 BSC 0_ 15 _ 0.25 1.02 INCHES MIN MAX 0.940 0.990 0.260 0.295 0.150 0.200 0.015 0.022 0.055 0.065 0.100 BSC 0.020 0.050 0.008 0.012 0.125 0.160 0.300 BSC 0_ 15_ 0.010 0.040
20 1
11 10
N H D
SEATING PLANE
G
K
J M
-A-
20 11
N SUFFIX PLASTIC PACKAGE CASE 738-03 ISSUE E
B
1
10
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
-A-
20 11
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 ISSUE E
10X
-B-
1 10
P 0.010 (0.25)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029
20X
D
M
0.010 (0.25)
TA
S
B
J
S
F R X 45 _ C -T-
18X SEATING PLANE
G
K
M
MOTOROLA
6
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC373A
OUTLINE DIMENSIONS
SD SUFFIX PLASTIC SSOP PACKAGE CASE 940C-03 ISSUE B
20X
K REF 0.12 (0.005)
M
TU
S
V
0.25 (0.010)
S
N M N
L/2 L
PIN 1 IDENT
20
11
B
1 10
F DETAIL E K J
0.20 (0.008)
M
TU
S
SECTION N-N -W-
0.076 (0.003) -T-
SEATING PLANE
C D G H
DETAIL E
20X
K REF
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
2X
L/2
20
11
L
PIN 1 IDENT 1 10
B -U-
J J1
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
High-Speed CMOS Logic Data DL129 -- Rev 6
7
IIII IIII IIII
EEE CCC EEE CCC
K1 K K1 DETAIL E
A -V-
-U-
J1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 7.07 7.33 5.20 5.38 1.73 1.99 0.05 0.21 0.63 0.95 0.65 BSC 0.59 0.75 0.09 0.20 0.09 0.16 0.25 0.38 0.25 0.33 7.65 7.90 0_ 8_ INCHES MIN MAX 0.278 0.288 0.205 0.212 0.068 0.078 0.002 0.008 0.024 0.037 0.026 BSC 0.023 0.030 0.003 0.008 0.003 0.006 0.010 0.015 0.010 0.013 0.301 0.311 0_ 8_
SECTION N-N
0.25 (0.010)
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
M
DIM A B C D F G H J J1 K K1 L M
-W-
MOTOROLA
MC54/74HC373A
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315
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8
MC74HC373A/D High-Speed CMOS Logic Data DL129 -- Rev 6

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